Semiconductor device assemblies, including, but not limited to, memory chips, microprocessor chips, and imager chips, typically include a semiconductor device, such as a die, mounted on a substrate, the semiconductor device assembly may be encased in a plastic protective covering or metal heat spreader. The semiconductor device assembly may include various functional features, such as memory cells, processor circuits, and imager devices, and may include bond pads that are electrically connected to the functional features of the semiconductor device assembly. The semiconductor device assembly may include semiconductor devices stacked upon and electrically connected to one another by individual interconnects between adjacent devices within a package.
Various methods and/or techniques may be employed to electrically interconnect adjacent semiconductor devices and/or substrates in a semiconductor device assembly. For example, individual interconnects may be formed by reflowing tin-silver (SnAg), also known as solder, to connect a pillar to a pad. Individual interconnects may be formed by reflowing various materials such as, but not limited to, tin-silver-copper solder, indium, or the like, as would be recognized by one of ordinary skill in the art having the benefit of this disclosure. Typically, the pillar may extend down from a bottom surface of a semiconductor device towards a pad formed on the top surface of another semiconductor device or substrate. A pillar may have a base portion comprised of copper (Cu) and an end portion comprised of solder. The pillar may include a layer of nickel (Ni) positioned between the copper portion and the solder portion, which acts as a barrier to prevent copper mixing and consumption by the solder during reflow and subsequently prevents electromigration of the solder into the copper during the solder reflow process. However, in some instances solder flows out and around the nickel barrier to the copper portion of the pillar, often referred to as solder slumping, which may lead to copper consumption, intermetallics (IMC) issues, and possible shorting between pillars.
Various methods and/or techniques may be employed to support adjacent dies and/or substrates in a semiconductor device assembly. For example, thermal compression bonding (TCB) with non-conductive film (NCF), which may include a wafer level underfill (WLUF), is a technique that may be used to connect a semiconductor device to a substrate to create a semiconductor device assembly. As an example, underfill material, which may be a laminated sheet of film, is deposited onto a wafer comprising multiple dies. The wafer may be diced to form individual dies that are then bonded to a substrate. One potential disadvantage of WLUF is the presence of voids due to the topography (e.g., copper traces, solder mask) of the substrate. For example, the topography may inhibit WLUF from flowing outside the die area.
When forming a semiconductor device assembly it may be desired to have a specific bond line between the semiconductor device and the substrate or adjacent semiconductor device. During the bonding process, the force applied during the bonding process may need to be varied in an attempt to obtain the specified bond line. For example, when the NCF material is at a high viscosity state a higher force may need to be applied to obtain the desired bond line, but as the NCF is heated during the TCB process the viscosity of the NCF may decrease so that less force is required to obtain the desired bond line. The change in viscosity during the TCB process, which in turn causes a variation in the applied force may make it difficult to consistently obtain the desired bond line for the duration of the process.
A higher force applied during the TCB process may help to eliminate the WLUF voids, but the higher applied force may cause solder to unintentionally bridge across traces and/or interconnects of the semiconductor device assembly as would be appreciated by one of ordinary skill in the art. Alternatively, the solder thickness may be reduced to help eliminate bridging, but a reduced solder thickness may lead to metastable IMC issues as would be recognized by one of ordinary skill in the art.
Additional drawbacks and disadvantages may exist.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the intention is to cover all modifications, equivalents and alternatives falling within the scope of the disclosure as defined by the appended claims.